In response to an increased need for smaller electronic devices with denser circuits, devices with three dimensional (3D) structures have been developed. An example of such devices includes FinFETs having conductive fin-like structures that are raised vertically above the horizontally extending substrate. Referring to FIG. 1a, there is shown a perspective view of a conventional FinFET 100 formed on a substrate 102. The substrate 102 may comprise, for example, a semiconducting substrate, or silicon-on-insulator. In one example, the substrate 102 may comprise a semiconducting substrate 102a and an oxide layer 102b disposed on the semiconducting substrate 102a. FinFET 100 may also comprise a source region 112 and drain region 114 that are connected to one another by a fin structure 116 serving as the channels. For convenience, FIG. 1a shows FinFET device 100 with only two fin structures 116. However, those of ordinary skill in the art will recognize that other FinFET devices may contain a single fin structure, or three or more fin structures. The conventional FinFET device 100 may also include a gate structure 122 formed across the fin structures 116, and a gate dielectric 124 that electrically isolates the gate structure 122 from the fin structure 116. In the conventional FinFET device 100, the surface area of the fin structure 116 in contact with gate dielectric 124 may be the effective channel region. Referring to FIG. 1b, there is shown a cross sectional view of the FinFET 100 shown in FIG. 1a. For convenience, the source region 112 and the drain region 114 are omitted from the figure. As illustrated, the fin structures 116 may extend vertically from the substrate 102. In another example, the fin structures may be disposed above the oxide layer so that it is electrically isolated from the semiconducting substrate.
Referring to FIG. 2a-2f, there is shown a conventional method for manufacturing FinFET device 100 having fin structures 116 shown in FIG. 1. As illustrated in FIG. 2a, a substrate 202 such as a silicon wafer may be provided. On the substrate 202, a layer of hardmask 204 is formed (FIG. 2b). Thereafter, a layer of photoresist may be deposited onto the hardmask 204. After depositing the resist, the photoresist may be patterned. As known in the art, various methods including photolithography may be used to pattern the photoresist 206. Thereafter, the pattern of the resist 206 may be transferred onto the hardmask 204 and a portion of the substrate 202 via an etching process. The resulting structure may include the patterned hardmask 204 and fin structure 210 corresponding to the pattern of the photoresist 206, as illustrated in FIG. 2c. Those skilled in the art will recognize that the fins structures 210 formed in this process may be the fin structure 116 shown in FIGS. 1a and 1b. An oxide layer 220, such as SiO2, may be deposited on the substrate, as shown in FIG. 2d. Thereafter, a chemical-mechanical polishing/planarization (CMP) process may be performed to planarize the resulting structure (FIG. 2e). As illustrated in FIG. 2e, the CMP process may be performed until either the patterned hardmask 204 or the fin structure 210 is exposed. After the CMP process, a wet or dry etching process may performed to remove a portion of the oxide layer 210 until the sidewalls of the fin structures 210 are exposed (FIG. 2f). The structure that may be formed after the etching process may include a substrate 202, the oxide layer 220, and one or more fin structures 210 extending above the oxide layer 220.
The above process, although adequate, contains several shortcomings. One of such shortcomings may found in the uniformity of oxide layer 220 and the fin structures 210. In particular, the etching process used to expose the fin structures 210 may be a non-uniform process with non-uniform etch rate across the substrate 202. The oxide layer 220 in one part of the substrate 202 may be etched at a greater rate compared to the other parts of the substrate 202. Accordingly, the oxide layer 220, with varying thickness, may form.
In addition, the fin structures 210 in one part of the substrate 202 may be exposed before fin structures 210 in other parts of the substrate 202. Moreover, the fin structures 210 exposed earlier part of the etch process may be exposed to etchants for longer period of time. Ultimately, the fin structures 210 with non-uniform widths and heights may form across the substrate 202. Other processes including CMP process may also contribute to a non-uniform oxide layer 220 and fin structures 210. Moreover, the etching process used to expose the fin structures 210 is a timed etching process with a great number of variables. A slight variation in the etching process may result in reduced repeatability or increased substrate-to-substrate non-uniformity. The fin structures 210 on different substrates 202 may have different height and/or width. As the performance of the FinFET devices may be influenced by the properties of the fin structures 210, it may be desirable to form more uniform fin structures 210. As such, uniformity and repeatability of the process used to form the fin structures are highly desirable.
Further, if a wet etching process is used to expose the fin structure 210, a phenomenon such as corner rounding 211 may occur. Such a phenomenon may contribute to less than optimal performance of the FinFET devices.
Accordingly, a new method for forming the fin structure is needed.